Aluminum (Al) has mainly been used as an interconnection line material for a semiconductor device in the past. However, copper (Cu) has been recently used as an interconnection line material instead of Al, because the integration density and the speed of semiconductor devices have increased, so the line width of the interconnection lines has been reduced, thereby decreasing their resistance and contact resistance and reducing occurrence of electro migration (EM), is disclosed in U.S. Pat. No. 6,198,170.
As Cu has low resistivity and high resistance against EM compared with Al, it can provide high reliability when used an interconnection line for a high integration density device and a high-speed device. On the other hand, as it is impossible to pattern Cu by dry etching, to form a Cu interconnection line, a dual damascene process is used to form a via hole and a trench in an intermediate insulating layer, the via hole and the trench are filled with Cu, and a planarization process must be performed.
A known method of forming an interconnection line for a semiconductor device is described with reference to FIG. 1A to FIG. 1G. As shown in FIG. 1A, a semiconductor substrate 10 on which a lower insulating layer 11 and a first interconnection line 12 are formed, is provided. An etch stop layer 13 is then formed on the entire surface of the substrate, and an intermediate insulating layer 14 of an oxide layer is formed on the etch stop layer 13.
As shown in FIG. 1B, a first photoresist pattern (not shown) is formed on the intermediate insulating layer 14 by a photolithography process, and the intermediate insulating layer 14 is then etched by an etching process using the first photoresist pattern as an etching mask, to form a via hole 15 exposing the portion of the etch stop layer 13 over the first interconnection line 12. Thereafter, the first photoresist pattern is removed by a well-known method.
As shown in FIG. 1C, a sacrificial layer 16 is formed on the intermediate insulating layer 14 to fill the via hole 15. The sacrificial layer 16 is then removed to expose the intermediate insulating layer and to form a recess over the sacrificial layer 16 of the via hole 15. The sacrificial layer 16 is formed of a photoresist layer.
As shown in FIG. 1D, a second photoresist pattern 17 is formed on the intermediate insulating layer 14 by a photolithography process, and the portion of the intermediate insulating layer 14 is then etched by an etching process using the second photoresist pattern 17 as an etch mask, to form a trench 18 including the via hole 15 at the upper portion of the via hole 15.
As shown in FIG. 1E, the second photoresist pattern 17 is removed by a well-known method. At this time, the sacrificial layer 16 is also removed, to expose the etch stop layer 13 at the bottom of the via hole 15.
As shown in FIG. 1F, the exposed portion of the etch stop layer 13 is removed, to expose the first interconnection layer 12 at the bottom of the via hole 15.
As shown in FIG. 1G, a Cu layer is formed on the intermediate insulating layer 14 to fill the via hole 15 and the trench 18, and a planarization process is then performed to expose the intermediate insulating layer 14, thereby forming a second interconnection line 19 that is electrically connected to the first interconnection line 12.
In the known method of forming the interconnection line as described above, when forming the via hole 15, the etch stop layer 13 stops the intermediate insulating layer 14 from being etched to prevent damage to the first interconnection line 12 due to the etching. Therefore, a material having high etch selectivity to the intermediate insulating layer 14 such as, for example, a nitride layer must be used as the etch stop layer 13.
However, the nitride layer has problems in that RC delay increases and the speed of a device manufactured thereby is deteriorated because it has a relatively high dielectric constant (high-k) compared with the oxide layer. To overcome these problems, an insulating layer of a low dielectric constant (low-k) has been used as the intermediate insulating layer 14, but it is difficult to obtain good effects if the etch stop layer 13 at the bottom of the via hole 15 is not fully removed.
Here, the etch stop layer 13 remains at the bottom of the via hole 15 because a polymer (not shown) remains over the sacrificial layer 16 when etching the intermediate insulating layer 14 for forming the trench 18, and this prevents the sacrificial layer 16 from being removed when removing the second photoresist pattern 17 for the sacrificial layer 16 to remain in the via hole 15, so that the etch stop layer 13 is not fully removed when removing the etch stop layer 13.
Accordingly, to prevent the etch stop layer 13 from remaining at the bottom of the via hole 15, the sacrificial layer 16 remaining in the via hole 15 must be fully removed by additionally performing a washing or a post etch treatment (PET), but there is problem in that this causes process time and fabrication cost to increase.